元器件交易网www.cecb2b.com SN54HC132, SN74HC132QUADRUPLE POSITIVE-NAND GATESWITH SCHMITT-TRIGGER INPUTSSCLS034C – DECEMBER 1982 – REVISED MAY 1997DOperation From Very Slow InputDDDDTransitionsTemperature-Compensated ThresholdLevelsHigh Noise ImmunitySame Pinouts as ’HC00Package Options Include PlasticSmall-Outline (D), Shrink Small-Outline(DB), and Ceramic Flat (W) Packages,Ceramic Chip Carriers (FK), and StandardPlastic (N) and Ceramic (J) 300-mil DIPsSN54HC132...J OR W PACKAGESN74HC132...D, DB, OR N PACKAGE(TOP VIEW)1A1B1Y2A2B2YGND1234567141312111098VCC4B4A4Y3B3A3Y descriptionEach circuit functions as a NAND gate, butbecause of the Schmitt action, it has different inputthreshold levels for positive- and negative-goingsignals. The ’HC132 perform the Boolean functionY = A • B or Y = A + B in positive logic.These circuits are temperature compensated andcan be triggered from the slowest of input rampsand still give clean jitter-free output signals.The SN54HC132 is characterized for operationover the full military temperature range of –55°Cto 125°C. The SN74HC132 is characterized foroperation from –40°C to 85°C.FUNCTION TABLE(each gate)INPUTSAHLXBHXLOUTPUTYLHHSN54HC132...FK PACKAGE(TOP VIEW)1B1ANCVCC4B1YNC2ANC2B45678321201918171615149101112134ANC4YNC3BNC – No internal connectionPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.Copyright © 1997, Texas Instruments IncorporatedPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•2YGNDNC3Y3A1元器件交易网www.cecb2b.comSCLS034C – DECEMBER 1982 – REVISED MAY 1997SN54HC132, SN74HC132QUADRUPLE POSITIVE-NAND GATESWITH SCHMITT-TRIGGER INPUTSlogic symbol†1A1B2A2B3A3B4A4B12459101213114Y83Y62Y&31Y †This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.Pin numbers shown are for the D, DB, J, N, and W packages.logic diagram (positive logic)AYBabsolute maximum ratings over operating free-air temperature range‡Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 VInput clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mAOutput clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mAContinuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mAContinuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mAPackage thermal impedance, θJA (see Note 2):D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/WDB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/WN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/WStorage temperature range, Tstg –65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 150°C‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTES:1.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.2.The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a tracelength of zero.2POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com SN54HC132, SN74HC132QUADRUPLE POSITIVE-NAND GATESWITH SCHMITT-TRIGGER INPUTSSCLS034C – DECEMBER 1982 – REVISED MAY 1997recommended operating conditionsSN54HC132MINVCCVIHSupply voltageHigh-level input voltageVCC = 2 VVCC = 4.5 VVCC = 6 VVCC = 2 VVILVIVOTALow-level input voltageInput voltageOutput voltageOperating free-air temperatureVCC = 4.5 VVCC = 6 V21.53.154.200000–550.51.351.8VCCVCC125NOM5MAX6SN74HC132MIN21.53.154.200000–400.51.351.8VCCVCC85VV°CVVNOM5MAX6UNITVelectrical characteristics over recommended operating free-air temperature range (unlessotherwise noted)PARAMETERTESTCONDITIONSTEST CONDITIONSVCC2 VIOH = –20 µAVOHVI = VIH or VILIOH = –4 mAIOH = –5.2 mAIOL = 20 µAVOLVI = VIH or VILIOL = 4 mAIOL = 5.2 mAVT+4.5 V6 V4.5 V6 V2 V4.5 V6 V4.5 V6 V2 V4.5 V6 V2 VVT–4.5 V6 V2 VVT+ – VT–IIICCCiVI = VCC or 0VI = VCC or 0,4.5 V6 V6 VIO = 06 V2 V to 6 V30.71.552.10.30.91.20.20.40.5TA = 25°CMINTYPMAX1.94.45.93.985.481.9984.4995.9994.35.80.0020.0010.0010.170.151.22.53.30.61.620.60.91.3±0.10.10.10.10.260.261.53.154.212.453.21.22.12.5±1002100.71.552.10.30.91.20.20.40.5SN54HC132MIN1.94.45.93.75.20.10.10.10.40.41.53.154.212.453.21.22.12.5±100040100.71.552.10.30.91.20.20.40.5MAXSN74HC132MIN1.94.45.93.845.340.10.10.10.330.331.53.154.212.453.21.22.12.5±10002010nAµApFVVVVVMAXUNITPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•3元器件交易网www.cecb2b.comSCLS034C – DECEMBER 1982 – REVISED MAY 1997SN54HC132, SN74HC132QUADRUPLE POSITIVE-NAND GATESWITH SCHMITT-TRIGGER INPUTS switching characteristics over recommended operating free-air temperature range, CL = 50 pF(unless otherwise noted) (see Figure 1)PARAMETERFROM(INPUT)A or BTO(OUTPUT)YVCC2 Vtpd4.5 V6 V2 VttAny4.5 V6 VTA = 25°CMINTYPMAX60181428861202521751513SN54HC132MINMAX18637321102219SN74HC132MINMAX1563127951916nsnsUNIToperating characteristics, TA = 25°CPARAMETERCpdPower dissipation capacitance per gateTEST CONDITIONSNo loadTYP20UNITpFPARAMETER MEASUREMENT INFORMATIONFrom OutputUnder TestTestPointCL = 50 pF(see Note A)In-PhaseOutputInput50%tPLH50%10%tPHLOut-of-PhaseOutput90%50%10%tf90%trInput50%10%90%trVOLTAGE WAVEFORMINPUT RISE AND FALL TIMES90%VCC50%10%0 VtftPLH50%10%90%tr50%tPHL90%VOH50%10%VOLtfVOHVOLVCC0 VLOAD CIRCUITVOLTAGE WAVEFORMSPROPAGATION DELAY AND OUTPUT TRANSITION TIMESNOTES:A.CL includes probe and test-fixture capacitance.B.Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the followingcharacteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.C.The outputs are measured one at a time with one input transition per measurement.D.tPLH and tPHL are the same as tpd.Figure 1. Load Circuit and Voltage Waveforms4POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com
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