6812A6812xALOADSUPPLYSERIALDATA OUTOUT20OUT19OUT18OUT17OUT16OUT15OUT14OUT13OUT12OUT11BLANKINGGROUND123456VBBVDD282726252423LOGICSUPPLYSERIALDATA INOUT1OUT2OUT3OUT4OUT5OUT6OUT7OUT8OUT9OUT10STROBECLOCKDABiC-IV, 20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
The A6812– devices combine a 20-bit CMOS shift register,
accompanying data latches and control circuitry with bipolar sourcingoutputs and pnp active pull downs. Designed primarily to drive
vacuum-fluorescent displays, the 60 V and -40 mA output ratings alsoallow these devices to be used in many other peripheral power driverapplications. The A6812– features an increased data input rate (com-pared with the older UCN/UCQ5812-F) and a controlled output slewrate.
The CMOS shift register and latches allow direct interfacing withmicroprocessor-based systems. With a 3.3 V or 5 V logic supply, theywill operate to at least 10 MHz.
A CMOS serial data output permits cascade connections in applica-tions requiring additional drive lines. Similar devices are available asthe A6809– and A6810– (10 bits), A6811– (12 bits), and A6818– (32bits).
The A6812– output source drivers are npn Darlingtons, capable ofsourcing up to 40 mA. The controlled output slew rate reduces electro-magnetic noise, which is an important consideration in systems thatinclude telecommunications and/or microprocessors and to meet
government emissions regulations. For inter-digit blanking, all outputdrivers can be disabled and all sink drivers turned on with a BLANK-ING input high. The pnp active pull-downs will sink at least 2.5 mA.Two temperature ranges are available for optimum performance incommercial (suffix S-) or industrial (suffix E-) applications. Packagestyles are provided for through-hole DIP (suffix -A), surface-mountSOIC (suffix -LW), or minimum-area surface-mount PLCC (suffix-EP). Copper lead frames, low logic-power dissipation, and low
output-saturation voltages allow these drivers to source 25 mA from alloutputs continuously to more than +43°C (suffix -LW), +61°C (suffix-EP), or +77°C (suffix -A).
Data Sheet26182.126AREGISTERREGISTERLATCHESLATCHES71011121314BLNK222120191817STCLK28162715Dwg. PP-029-7ABSOLUTE MAXIMUM RATINGSat TA = 25°CLogic Supply Voltage, VDD................... 7.0 VDriver Supply Voltage, VBB................... 60 VContinuous Output Current Range,IOUT......................... -40 mA to +15 mAInput Voltage Range,VIN....................... -0.3 V to VDD + 0.3 VPackage Power Dissipation,PD........................................ See GraphOperating Temperature Range, TA(Suffix ‘E–’).................. -40°C to +85°C(Suffix ‘S–’).................. -20°C to +85°CStorage Temperature Range,TS............................... -55°C to +125°CCaution: These CMOS devices have input staticprotection (Class 2) but are still susceptible todamage if exposed to extremely high staticelectrical charges.FEATURES
I Controlled Output Slew RateI Low Output-Saturation VoltagesI High-Speed Data StorageI Low-Power CMOS LogicI 60 V Minimumand LatchesOutput BreakdownI Improved ReplacementsI High Data Input Ratefor TL5812–, UCN5812–,I PNP Active Pull-Downsand UCQ5812–Complete part number includes a suffix to identify operatingtemperature range (E- or S-) and package type (-A, -EP, or -LW).Always order by complete part number, e.g., A6812SLW.
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681220-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
A6812xEP
SERIALDATA OUTLOGICSUPPLYLOADSUPPLYSERIALDATA INOUT20OUT19OUT1 LOADSUPPLYSERIALDATA OUT
OUT20
123456REGISTERREGISTERLATCHESLATCHES71011121314BLNKSTCLKVBBA6812xLW
VDD28272625242322212019181728162715LOGIC
SUPPLYSERIALDATA INOUT1OUT2OUT3OUT4OUT5OUT6OUT7OUT8OUT9OUT10STROBECLOCK
VDD28VBB272321OUT18 562524OUT2OUT19OUT18OUT17OUT16OUT15OUT14
REGISTERREGISTERLATCHESLATCHES710OUT12 112322212019OUT8 OUT13OUT12
CLK1214ST1713151618OUT11GROUNDBLANKINGSTROBECLOCKOUT10OUT9OUT11BLANKING
Dwg. PP-059-1GROUND
TYPICAL INPUT CIRCUIT
Dwg. PP-029-8VDDALLOWABLE PACKAGE POWER DISSIPATION IN WATTS2.5SUFFIX 'EP', R θ JA = 55°C/WSUFFIX 'LW', R θ J =A 66°C/WINWC/5° 4 = θJA', R 'AIXFFSU2.01.5Dwg. EP-010-5TYPICAL OUTPUT DRIVERVBB1.00.5OUTN0255075100125AMBIENT TEMPERATURE IN °C150Dwg. EP-021-19Dwg. GP-024-2115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000Copyright © 2000, Allegro MicroSystems, Inc.
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20-BIT SERIAL-INPUT,LATCHED SOURCE DRIVER
6812FUNCTIONAL BLOCK DIAGRAMCLOCKSERIALDATA INSTROBESERIAL-PARALLEL SHIFT REGISTERVDDLOGICSUPPLYSERIALDATA OUT LATCHES BLANKINGMOSBIPOLARVBBLOADSUPPLYGROUNDOUT1OUT2OUT3OUTNDwg. FP-013-1 TRUTH TABLE
Serial Shift Register ContentsDataClockInputInputI1I2I3...IN-1INHLXHLR1R2...R1R2...RN-2RN-1RN-2RN-1RN-1RNXXSerialDataStrobeOutputInputRN-1RN-1RNXPNLHR1R2R3...P1P2P3...XXX...RN-1 RNPN-1 PNXXLHP1P2P3...PN-1 PNLLL...L LLatch ContentsI1I2I3...IN-1 Output ContentsINBlanklngI1I2I3... IN-1 INR1R2R3...XXX...P1P2P3...PN-1PNL = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
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681220-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25°C (A6812S-) or over operating temperaturerange (A6812E-), VBB = 60 V unless otherwise noted.
Limits @ VDD = 3.3 V Limits @ VDD = 5 V
Characteristic
Output Leakage CurrentOutput Voltage
SymbolICEXVOUT(1)VOUT(0)
Output Pull-Down CurrentInput Voltage
IOUT(0)VIN(1)VIN(0)
Input Current
IIN(1)IIN(0)
Input Clamp VoltageSerial Data Output Voltage
VIKVOUT(1)VOUT(0)
Maximum Clock FrequencyLogic Supply Current
fcIDD(1)IDD(0)
Load Supply Current
IBB(1)IBB(0)
Blanking-to-Output Delay
tdis(BQ)ten(BQ)
Strobe-to-Output Delay
tp(STH-QL)tp(STH-QH)
Output Fall TimeOutput Rise TimeOutput Slew Rate
tftrdV/dt
All Outputs HighAll Outputs Low
All Outputs High, No LoadAll Outputs LowCL = 30 pF, 50% to 50%CL = 30 pF, 50% to 50%RL = 2.3 kΩ, CL ≤ 30 pFRL = 2.3 kΩ, CL ≤ 30 pFRL = 2.3 kΩ, CL ≤ 30 pFRL = 2.3 kΩ, CL ≤ 30 pFRL = 2.3 kΩ, CL ≤ 30 pFIOUT = ±200 µAVIN = VDDVIN = 0 VIIN = -200 µAIOUT = -200 µAIOUT = 200 µATest ConditionsVOUT = 0 VIOUT = -25 mAIOUT = 1 mAVOUT = 5 V to VBB
Mln.—57.5—2.52.2————2.8—10*————————2.42.44.0—
Typ.<-0.158.31.05.0——<0.01<-0.01-0.83.050.15—0.250.253.00.20.71.80.71.8———50
Max.-15—1.5——1.11.0-1.0-1.5—0.3—0.750.756.0202.03.02.03.0121220—
Min.—57.5—2.53.3————4.5—10*————————2.42.44.0—
Typ.<-0.158.31.05.0——<0.01<-0.01-0.84.750.15—0.30.33.00.20.71.80.71.8———50
Max.-15—1.5——1.71.0-1.0-1.5—0.3—1.01.06.0202.03.02.03.0121220—
UnitsµAVVmAVVµAµAVVVMHzmAmAmAµAµsµsµsµsµsµsV/µsns
Clock-to-Serial Data Out Delaytp(CH-SQX)
Negative current is defined as coming out of (sourcing) the specified device terminal.Typical data is is for design information only and is at TA = +25°C.
* Operation at a clock frequency greater than the specified minimum is possible but not warranteed.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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20-BIT SERIAL-INPUT,LATCHED SOURCE DRIVER
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
CCLOCKASERIALDATA INDATA50%6812B50%t p(CH-SQX)SERIALDATA OUTDSTROBE50%50%DATAEBLANKING LOW = ALL OUTPUTS ENABLED t p(STH-QH)t p(STH-QL)OUTN90%10%DATADwg. WP-029 HIGH = ALL OUTPUTS BLANKED (DISABLED)BLANKING50%tdis(BQ)ten(BQ)OUTNtr90%10%tfDATADwg. WP-030A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D)...................................... 25 nsB. Data Active Time After Clock Pulse
(Data Hold Time), th(D)............................................ 25 nsC. Clock Pulse Width, tw(CH)............................................ 50 nsD. Time Between Clock Activation and Strobe, tsu(C).... 100 nsE. Strobe Pulse Width, tw(STH).......................................... 50 nsNOTE – Timing is representative of a 10 MHz clock. Higherspeeds may be attainable with increased supply voltage;operation at high temperatures will reduce the specifiedmaximum clock frequency.
data information towards the SERIAL DATA OUTPUT. TheSERIAL DATA must appear at the input prior to the rising edgeof the CLOCK input waveform.
Information present at any register is transferred to therespective latch when the STROBE is high (serial-to-parallelconversion). The latches will continue to accept new data aslong as the STROBE is held high. Applications where thelatches are bypassed (STROBE tied high) will require that theBLANKING input be high during serial data entry.
When the BLANKING input is high, the output sourcedrivers are disabled (OFF); the pnp active pull-down sinkdrivers are ON. The information stored in the latches is not
affected by the BLANKING input. With the BLANKING inputlow, the outputs are controlled by the state of their respectivelatches.
Serial Data present at the input is transferred to the shiftregister on the logic “0” to logic “1” transition of the CLOCKinput pulse. On succeeding CLOCK pulses, the registers shift
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681220-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
A6812EA & A6812SA
Dimensions in Inches(controlling dimensions)
0.0150.00828150.7000.5800.485MAX0.600BSC120.0700.030341.5651.380140.100BSC0.005MIN0.250MAX0.015MIN0.2000.1150.0220.014Dwg. MA-003-28 in Dimensions in Millimeters(for reference only)
28150.3810.20417.7814.7312.32MAX15.24BSC121.770.773439.735.1142.54BSC0.13MIN6.35MAX0.39MIN5.082.930.5580.356Dwg. MA-003-28 mmNOTES:1.
2.3.4.Exact body and lead configuration at vendor’s option within limits shown.Lead spacing tolerance is non-cumulative.
Lead thickness is measured at seating plane or below.Supplied in standard sticks/tubes of 12 devices.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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20-BIT SERIAL-INPUT,LATCHED SOURCE DRIVER
A6812EEP & A6812SEP
(add “TR” to part number for tape and reel)
Dimensions in Inches(controlling dimensions)
181268120.0130.0210.2190.19119110.0260.0320.4560.450BSCINDEX AREA0.0500.2190.1910.4950.485 255260.020MIN28140.1650.1800.4560.4500.4950.485 Dwg. MA-005-28A inDimensions in Millimeters(for reference only))
18120.3310.5335.5.8519111.27BSC0.8120.66111.5811.4312.5712.32 25INDEX AREA5.5.855260.51MIN28144.574.2011.58211.43012.5712.32 Dwg. MA-005-28A mmNOTES:1.Exact body and lead configuration at vendor’s option within limits shown.
2.Lead spacing tolerance is non-cumulative.
3.Supplied in standard sticks/tubes of 38 devices or add “TR” to part number for tape and reel.
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681220-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
A6812ELW & A6812SLW
(add “TR” to part number for tape and reel)
Dimensions in Inches(for reference only)
28150.01250.00910.29920.29140.4190.3940.0500.0160.0200.0131230.71250.69690.050BSC0° TO 8°0.09260.10430.0040 MIN.Dwg. MA-008-28A inDimensions in Millimeters(controlling dimensions)
28150.320.237.607.4010.6510.001.270.400.510.331231.27BSC18.1017.700° TO 8°2.652.350.10 MIN.Dwg. MA-008-28A mmNOTES:1.Exact body and lead configuration at vendor’s option within limits shown.
2.Lead spacing tolerance is non-cumulative.
3.Supplied in standard sticks/tubes of 27 devices or add “TR” to part number for tape and reel.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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20-BIT SERIAL-INPUT,LATCHED SOURCE DRIVER
6812The products described here are manufactured under one or moreU.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time totime, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, ormanufacturability of its products. Before placing an order, the user iscautioned to verify that the information being relied upon is current.Allegro products are not authorized for use as critical componentsin life-support devices or systems without express written approval.The information included herein is believed to be accurate andreliable. However, Allegro MicroSystems, Inc. assumes no responsi-bility for its use; nor for any infringement of patents or other rights ofthird parties which may result from its use.
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681220-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
POWER
INTERFACE DRIVERS
Function
8-Bit (saturated drivers)8-Bit8-Bit8-Bit8-Bit
8-Bit (constant-current LED driver)8-Bit (DMOS drivers)8-Bit (DMOS drivers)8-Bit (DMOS drivers)10-Bit (active pull-downs)12-Bit (active pull-downs)
16-Bit (constant-current LED driver)20-Bit (active pull-downs)32-Bit (active pull-downs)32-Bit
32-Bit (saturated drivers)4-Bit
8-Bit8-Bit
8-Bit (DMOS drivers)8-Bit (DMOS drivers)
Unipolar Stepper Motor Translator/DriverAddressable 8-Bit Decoder/DMOS DriverAddressable 8-Bit Decoder/DMOS DriverAddressable 8-Bit Decoder/DMOS DriverAddressable 28-Line Decoder/Driver*†‡
Output Ratings*
SERIAL-INPUT LATCHED DRIVERS
-120 mA350 mA350 mA350 mA350 mA75 mA250 mA350 mA100 mA-25 mA-25 mA75 mA-25 mA-25 mA100 mA100 mA350 mA-25 mA350 mA100 mA250 mA1.25 A250 mA350 mA100 mA450 mA
50 V‡ 50 V80 V 50 V‡ 80 V‡17 V 50 V 50 V‡ 50 V 60 V 60 V17 V 60 V 60 V 30 V 40 V 50 V‡ 60 V 50 V‡ 50 V 50 V 50 V‡ 50 V 50 V‡ 50 V 30 V
555821582258415842627565956A5956B595
5810-F and 6809/105811 and 68116276
5812-F and 68125818-F and 6818583358325800581558016B2736273580462596A2596B2596817
Part Number†
PARALLEL-INPUT LATCHED DRIVERS
SPECIAL-PURPOSE DEVICES
Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits.Negative current is defined as coming out of (sourcing) the output.
Complete part number includes additional characters to indicate operating temperature range and package style.Internal transient-suppression diodes included for inductive-load protection.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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