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专利名称：A flip-flop
发明人：Mahant-Shett, Shivaling S.,Landers, Robert J.申请号：EP96108356.5申请日：19960524公开号：EP0744833A3公开日：19980107
专利附图：
摘要：A flip-flop circuit which includes a master section (1) having a pair of back toback connected inverters (5, 7) to form a latch circuit with their ground terminalsconnected together. The clock signal is coupled to the ground terminal of the inverters(5,7) to provide a negative gate to source voltage rather than an essentially zero gate to
source voltage as used in prior art inverters to insure full turn off of the inverter
transistors (40, 45) during their off periods and conserving power thereby. When the firstphase of the clock signal goes high, the signal on the data line is fed to one side of thelatch and the other side of the latch is coupled to ground or reference voltage. When thefirst phase of the clock then goes low, the signal from the data line is latched into thelatch of the master section (1) and the other side of that latch is decoupled from ground.Also, when the first phase of the clock signal goes low and the second phase of the clocksignal concurrently goes high, the signal latched in the latch of the master section (1) isfed to the slave section (3). The slave section (3) is identical to the master section (1)except that the clock signals received are of opposite phase or state to the clock signalsreceived by the master section (1) and the input to the slave section (3) is the signallatched into the latch of the master section (1). The signal stored in the latch of the slavesection (3) is the output of the flip-flop.
申请人：TEXAS INSTRUMENTS INCORPORATED
地址：13500 North Central Expressway Dallas Texas 75265 US
国籍：US
代理机构：Schwepfinger, Karl-Heinz, Dipl.-Ing.
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